Hardware-Efficient Triple Modular Redundancy via Shared Arithmetic Resources

DOI

https://www.doi.org/10.59256/ijire.20260704001

Published In

Volume 7, Issue 4 (2026)

Published Online

July-August 2026

Pages

01-06

Article Type

Original Article

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Conventional Triple Modular Redundancy (TMR) provides robust fault masking by triplicating functional logic and applying a two-out-of-three majority voter. Although this approach is effective against single faults and transient upsets, full replication of multiplier- intensive datapaths results in large area, power, and thermal overhead. This paper proposes a hardware-efficient resource-sharing TMR architecture that preserves the voting semantics of TMR while replacing three dedicated multipliers with a single low-power shared Booth-Wallace multiplier. The three redundant datapaths retain independent local logic, registers, and control state, while a round-robin arbiter and time-division multiplexing scheduler coordinate access to the shared arithmetic resource through request, grant, and done handshaking. Analytical evaluation indicates that the design can reduce normalized area from approximately 3.0x to 1.4-1.5x and normalized power from approximately 3.0x to 1.1-1.3x compared with conventional full TMR, while preserving deterministic masking of one faulty replica. The proposed approach is suitable for energy-constrained and mission-critical systems such as nanosatellites, portable avionics, embedded sensor processors, and implantable medical electronics.