Hardware-Efficient Triple Modular Redundancy via Shared Arithmetic Resources

B. Gayathiri; N. Peramlatha

doi:10.59256/ijire.20260704001

Original Article

Hardware-Efficient Triple Modular Redundancy via Shared Arithmetic Resources

Paper ID 1157
Volume 7, Issue 4
Pages 01-06
Published Online: July-August 2026
1 Views

Open Access Peer Reviewed Crossref DOI

Authors

B. Gayathiri¹
N. Peramlatha²

¹ VLSI Design, Vandayar Engineering College, Thanjavur, Tamilnadu, India. ² Assistant Professor, Vandayar Engineering College, Thanjavur, Tamilnadu, India.

View PDF Download PDF Cite this article

Article Information

DOI: https://www.doi.org/10.59256/ijire.20260704001
Published In: Volume 7, Issue 4 (2026)
Published Online: July-August 2026
Pages: 01-06
Article Type: Original Article
Check for updates

Citations

B. Gayathiri, N. Peramlatha, “Hardware-Efficient Triple Modular Redundancy via Shared Arithmetic Resources”, IJIRE-V7I4-01-06

Hardware-Efficient Triple Modular Redundancy via Shared Arithmetic Resources

Article Information

Citations

Related Articles