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- Vol. 7 Issue 4
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Hardware-Efficient Triple Modular Redundancy via Shared Arithmetic Resources
Authors
1 VLSI Design, Vandayar Engineering College, Thanjavur, Tamilnadu, India. 2 Assistant Professor, Vandayar Engineering College, Thanjavur, Tamilnadu, India.
Article Information
- Published In
- Volume 7, Issue 4 (2026)
- Published Online
- July-August 2026
- Pages
- 01-06
- Article Type
- Original Article
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