High-Throughput Low-Latency Pipelined Divider for Single Precision Floating-Point Numbers

DOI

No DOI

Published In

Volume 4, Issue 2 (2023)

Published Online

March-April 2023

Pages

218-223

Article Type

Research Article

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Abstract: IEEE Standard 754 floating point is the most prevalent format today for real numbers on computers. An overview of IEEE floating point and its representation is provided in this publication. In order to improve time and area performance, this study describes a single precision floating point divider. The main goal of this work is to create a specific method for splitting two floating point integers in order to decrease power consumption and boost execution speed. In comparison to earlier Dividers, this one is faster and more accurate because to the pipelining process. This Verilog-described pipelined design is built on a Xilinx Spartan 3 FPGA. Xilinx Timing Analyzer is used to assess timing performance. To reduce the critical path, a compressor and an adder also compute the total of the partial products and other data. The combined findings demonstrate that our design's highest attainable frequency is superior to that of the current approaches. Moreover, when compared to existing techniques, our concept clearly outperforms them in terms of latency and throughput.. This Design is implemented using Verilog HDL and simulated by Modelsim 6.4 c.