High-Throughput Low-Latency Pipelined Divider for Single Precision Floating-Point Numbers

Nidish kumar P; Abishek M; Dineshkumar v

Research Article

High-Throughput Low-Latency Pipelined Divider for Single Precision Floating-Point Numbers

Paper ID 397
Volume 4, Issue 2
Pages 218-223
Published Online: March-April 2023

Open Access Peer Reviewed

Authors

Nidish kumar P¹
Abishek M²
Dineshkumar v³

¹²³Electronics and communication engineering , Bannari Amman Institute of Technology, Tamil Nadu, India.

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DOI: No DOI
Published In: Volume 4, Issue 2 (2023)
Published Online: March-April 2023
Pages: 218-223
Article Type: Research Article
Check for updates: No DOI available for cross-reference

Citations

Nidish kumar P, Abishek M, Dineshkumar v, “High-Throughput Low-Latency Pipelined Divider forSingle Precision Floating-Point Numbers”, IJIRE-V4I02-218-223.

High-Throughput Low-Latency Pipelined Divider for Single Precision Floating-Point Numbers

Article Information

Citations

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