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Pulsed Latches Based Parallel Pipelined Architecture and Algorithm for MatrixTransposition
Authors
1 Student, M-tech in VLSI Design, ECE, IES College of Engineering, Chittilappilly, Kerala, India. 2Assistant Professor, Department of ECE, IES College of Engineering, Chittilappilly, Kerala, India.
Article Information
- DOI
- No DOI
- Organised By
- IES College of Engineering
- Conference Date
- 15 May 2023
- Pages
- 82-87
- Article Type
- Research Article
- Check for updates
- No DOI available for cross-reference
References
1. M. Bian, F. Bi, and F. Liu, “Matrix transpose methods for SAR imaging system,” in Proc. IEEE 10th Int. Conf. SignalProcess., Beijing,
China, Oct. 2010, pp. 2176–2179.
2. D. Im, D. Han, S. Choi, S. Kang, and H.-J. Yoo, “DT-CNN: An energyefficient dilated and transposed convolutional neural network
processor for region of interest based image segmentation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 10, pp. 3471–3483,
Oct. 2020.
3. F. Mahmood, M. Toots, L.-G. Öfverstedt, and U. Skoglund, “2D discrete Fourier transform with simultaneous edge artifact removal
for realtime applications,” in Proc. Int. Conf. Field Program. Technol. (FPT), Queenstown, New Zealand, 2015, pp. 236–239.
4. S. Murugan and K. Jayakumar, “A DSP based real-time 3D FFT system for analysis of dynamic parameters,” in Proc. IEEE Int. Conf.
Adv. Commun. Control Comput. Technol., Ramanathapuram, India, 2014, pp. 1489–1492
5. H. Song, “The application of computer vision in responding to the emergencies of autonomous driving,” in Proc. Int.Conf. Comput.
Vis. Image Deep Learn. (CVIDL), Chongqing, China, 2020, pp. 1–5.
6. A. Barnard, “The nursing profession: Implications for AI and natural language processing,” in Proc. Int. Conf. Natural Lang. Process.
Knowl. Eng., Beijing, China, 2007, pp. 497–501.
7. K. He, X. Zhang, S. Ren, and J. Sun, “Deep residual learning for image recognition,” in Proc. IEEE Conf. Comput.Vis. Pattern
Recognit. (CVPR), Las Vegas, NV, USA, 2016, pp. 770–778.
8. Y. Wang, Z. Ma, and F. Yu, “Pipelined algorithm and modular architecture for matrix transposition,” IEEE Trans.Circuits Syst. II,
Exp. Briefs, vol. 66, no. 4, pp. 652–656, Apr. 2019.
9. M. Garrido, J. Grajal, and O. Gustafsson, “Optimum circuits for bitdimension permutations,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 27, no. 5, pp. 1148–1160, May 2019.
10. M. Garrido and P. Pirsch, “Continuous-flow matrix transposition using memories,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67,
no. 9, pp. 3035–3046, Sep. 2020.
11. M. V. Noskov and V. S. Tutatchikov, “Modification of a two-dimensional fast Fourier transform algorithm by the analog of the Cooley–
Tukey algorithm for a rectangular signal,” Pattern Recognit. Image Anal., vol. 25, no. 1, pp. 81–83, Jan. 2015.
12. B. Zhang, Z. Ma, and F. Yu, “A novel pipelined algorithm and modular architecture for non-square matrix transposition,” IEEE
Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 4, pp. 1423–1427, Apr. 2021.
13. S. Yang, Z. Quan, M. Nie, and W. Yang, “TransPose: Keypoint localization via transformer, ” in Proc. IEEE/CVF Int. Conf. Comput.
Vis., 2021, pp. 11802–11812.
14. M. Garrido, J. Grajal, and O. Gustafsson, “Optimum circuits for bit reversal,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 58, no.
10, pp. 657–661, Oct. 2011.
15. C. Cheng and F. Yu, “An optimum architecture for continuous-flow parallel bit reversal,” IEEE Signal Process.Lett., vol. 22, no. 12,
pp. 2334–2338, Dec. 2015.
16. T. Järvinen, P. Salmela, H. Sorokin, and J. Takala, “Stride permutation networks for array processors,” J. VLSI Signal Process. Syst.Signal Image Video Technol., vol. 49, no. 1, pp. 51–71, 2007.
17. M. Garrido, J. Grajal, and O. Gustafsson, “Optimum circuits for bit reversal,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 58, no.
10, pp. 657–661, Oct. 2011.
18. L. Wei and J. Mellor-Crummey, “Autotuning tensor transposition,” in Proc. IEEE Int. Parallel Distrib. Process.Symp. Workshops
(IPDPSW), 2014, pp. 342–351.
19. J. O. Eklundh, “A fast computer method for matrix transposing,” IEEE Trans. Comput., vol. C-21, no. 7, pp. 801–803, Jul. 1972
20. S. Panchanathan, “Universal architecture for matrix transposition,” IEE Proc. E Comput. Digit. Tech., vol. 139,no. 5, pp. 387–392,
Sep. 1992.
21. M. R. Portnoff, “An efficient method for transposing large matrices and its application to separable processing of two-dimensional
signals,” IEEE Trans. Image Process., vol. 2, no. 1, pp. 122–124, Jan. 1993
China, Oct. 2010, pp. 2176–2179.
2. D. Im, D. Han, S. Choi, S. Kang, and H.-J. Yoo, “DT-CNN: An energyefficient dilated and transposed convolutional neural network
processor for region of interest based image segmentation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67, no. 10, pp. 3471–3483,
Oct. 2020.
3. F. Mahmood, M. Toots, L.-G. Öfverstedt, and U. Skoglund, “2D discrete Fourier transform with simultaneous edge artifact removal
for realtime applications,” in Proc. Int. Conf. Field Program. Technol. (FPT), Queenstown, New Zealand, 2015, pp. 236–239.
4. S. Murugan and K. Jayakumar, “A DSP based real-time 3D FFT system for analysis of dynamic parameters,” in Proc. IEEE Int. Conf.
Adv. Commun. Control Comput. Technol., Ramanathapuram, India, 2014, pp. 1489–1492
5. H. Song, “The application of computer vision in responding to the emergencies of autonomous driving,” in Proc. Int.Conf. Comput.
Vis. Image Deep Learn. (CVIDL), Chongqing, China, 2020, pp. 1–5.
6. A. Barnard, “The nursing profession: Implications for AI and natural language processing,” in Proc. Int. Conf. Natural Lang. Process.
Knowl. Eng., Beijing, China, 2007, pp. 497–501.
7. K. He, X. Zhang, S. Ren, and J. Sun, “Deep residual learning for image recognition,” in Proc. IEEE Conf. Comput.Vis. Pattern
Recognit. (CVPR), Las Vegas, NV, USA, 2016, pp. 770–778.
8. Y. Wang, Z. Ma, and F. Yu, “Pipelined algorithm and modular architecture for matrix transposition,” IEEE Trans.Circuits Syst. II,
Exp. Briefs, vol. 66, no. 4, pp. 652–656, Apr. 2019.
9. M. Garrido, J. Grajal, and O. Gustafsson, “Optimum circuits for bitdimension permutations,” IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 27, no. 5, pp. 1148–1160, May 2019.
10. M. Garrido and P. Pirsch, “Continuous-flow matrix transposition using memories,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 67,
no. 9, pp. 3035–3046, Sep. 2020.
11. M. V. Noskov and V. S. Tutatchikov, “Modification of a two-dimensional fast Fourier transform algorithm by the analog of the Cooley–
Tukey algorithm for a rectangular signal,” Pattern Recognit. Image Anal., vol. 25, no. 1, pp. 81–83, Jan. 2015.
12. B. Zhang, Z. Ma, and F. Yu, “A novel pipelined algorithm and modular architecture for non-square matrix transposition,” IEEE
Trans. Circuits Syst. II, Exp. Briefs, vol. 68, no. 4, pp. 1423–1427, Apr. 2021.
13. S. Yang, Z. Quan, M. Nie, and W. Yang, “TransPose: Keypoint localization via transformer, ” in Proc. IEEE/CVF Int. Conf. Comput.
Vis., 2021, pp. 11802–11812.
14. M. Garrido, J. Grajal, and O. Gustafsson, “Optimum circuits for bit reversal,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 58, no.
10, pp. 657–661, Oct. 2011.
15. C. Cheng and F. Yu, “An optimum architecture for continuous-flow parallel bit reversal,” IEEE Signal Process.Lett., vol. 22, no. 12,
pp. 2334–2338, Dec. 2015.
16. T. Järvinen, P. Salmela, H. Sorokin, and J. Takala, “Stride permutation networks for array processors,” J. VLSI Signal Process. Syst.Signal Image Video Technol., vol. 49, no. 1, pp. 51–71, 2007.
17. M. Garrido, J. Grajal, and O. Gustafsson, “Optimum circuits for bit reversal,” IEEE Trans. Circuits Syst. II, Exp.Briefs, vol. 58, no.
10, pp. 657–661, Oct. 2011.
18. L. Wei and J. Mellor-Crummey, “Autotuning tensor transposition,” in Proc. IEEE Int. Parallel Distrib. Process.Symp. Workshops
(IPDPSW), 2014, pp. 342–351.
19. J. O. Eklundh, “A fast computer method for matrix transposing,” IEEE Trans. Comput., vol. C-21, no. 7, pp. 801–803, Jul. 1972
20. S. Panchanathan, “Universal architecture for matrix transposition,” IEE Proc. E Comput. Digit. Tech., vol. 139,no. 5, pp. 387–392,
Sep. 1992.
21. M. R. Portnoff, “An efficient method for transposing large matrices and its application to separable processing of two-dimensional
signals,” IEEE Trans. Image Process., vol. 2, no. 1, pp. 122–124, Jan. 1993
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