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Pulsed Latches Based Parallel Pipelined Architecture and Algorithm for MatrixTransposition
Authors
1 Student, M-tech in VLSI Design, ECE, IES College of Engineering, Chittilappilly, Kerala, India. 2Assistant Professor, Department of ECE, IES College of Engineering, Chittilappilly, Kerala, India.
Article Information
- DOI
- No DOI
- Organised By
- IES College of Engineering
- Conference Date
- 15 May 2023
- Pages
- 82-87
- Article Type
- Research Article
- Check for updates
- No DOI available for cross-reference
Citations
Shaheela A M, Anitta Antony,”Pulsed Latches Based Parallel Pipe lined Architecture and Algorithm for Matrix Transposition”, IJIRE-V4I03-82-87.
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