Pulsed Latches Based Parallel Pipelined Architecture and Algorithm for MatrixTransposition

DOI

No DOI

Conference

Innovations in Computing, Materials and Communication Technologies

Organised By

IES College of Engineering

Conference Date

15 May 2023

Pages

82-87

Article Type

Research Article

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This paper proposes a new algorithm and architecture for continuous flow matrix transposition using pulsed latches. The algorithm supports P-parallel matrix transposition. The hardware architecture reaches the theoretical minimum in terms of memory and latency. Low power consumption and area efficiency is the most advantage of using pulsed latches. Instead of using conventional single pulsed clock signals, here we use multiple non overlap delayed pulsed clock signals in order to reduce the timing problems between pulsed latches. Compared with the state-of-the-art architecture, the proposed architecture supports matrices whose rows and columns are integer multiples of P. Here P can be arbitrary, including but not limited to power-of-two-integers. More over our result provide additional insight into continuous flow non-square matrix transposition.