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Research Article

Approximate Multipliers Using Static and Dynamic Segmentation: Area, Delay and Power Comparison

  • ICICMCT'23
  • Volume 4, Issue 3
  • Pages 53-56
  • Published Online: 2023
Open Access Peer Reviewed

Authors

  • Suvitha P S1
  • Varsha Viji VS2

1Assistant Professor, ECE, IES College of Engineering, Chittilappilly, Kerala, India. 2Student, MTech VLSI, IES College of Engineering, Chittilappilly, Kerala, India.

Article Information

DOI
No DOI
Organised By
IES College of Engineering
Conference Date
15 May 2023
Pages
53-56
Article Type
Research Article
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References

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effectiveness, ” in Proc. 52nd Annu. Design Autom.Conf.,Jun. 2015,pp. 1 – 6.
2. Q. Xu,M. Todd, andS.K. Nam, “ Approximation computing A check of multipliers, ” IEEE Design Test,vol. 33,no. 1,pp. 8 – 22,Feb. 2016.
3. W. Liu,F. Lombardi, andM. Schulte, “ A retrospective prospective view of approximation computing, ” Proc. IEEE,vol. 108,no. 3,pp. 394
– 399,Mar. 2020.
4. H. Jiang,F.J.H. Santiago,H. Mo,L. Liu, andJ. Han, “ Approximation computation circuits A check and characterization, and recent
operations, ” Proc. IEEE,vol. 108,no. 12,pp. 2108 – 2135,Dec. 2020.
5. W. Liu,J. Xu,D. Wang,C. Wang,P. Montuschi, andF. Lombardi, “ Design and valuation of approximate logarithmic multipliers for low
power error-tolerant operations, ” IEEE Trans. Circuits Syst. I, Reg. Papers,vol. 65,no. 9,pp. 2856 – 2868,Sep. 2018.
6. M.S. Ansari,B.F. Cockburn, andJ. Han, “ An advanced fashion of logarithmic multiplier for energy-effective neural computing, ” IEEE
Trans.Comput.,vol. 70,no. 4,pp. 614 – 625,Apr. 2021.
7. R. Pilipovic,P. Bulic, andU. Lotric, “ A two- stage operand and its trouncing approximate logarithmic multiplier, ” IEEE Trans. Circuits
Syst. I, Reg. Papers,vol. 68,no. 6,pp. 2535 – 2545,Jun. 2021.
8. M.S. Kim,A.A.D. Barrio,L.T. Oliveira,R. Hermida, andN. Bagherzadeh, “ Effective further and further Mitchell’s approximate log
multipliers for convolutional neural networks, ” IEEE Trans.Comput.,vol. 68,no. 5,pp. 660 – 675, May 2019.
9. P. Kulkarni,P. Gupta, andM. Ercegovac, “ Trading delicacy for power with an under designed multiplier armature, ” in Proc. 24th Int.
Conf. VLSI Design,Jan. 2011,pp. 346 – 351.
10. S. Rehman,W. El- Harouni,M. Shafique,A. Kumar, andJ. Henkel, “ Architectural- space disquisition of approximate multipliers, ” in
Proc. 35th Int. Conf.Comput.- backed Design,Nov.2016,pp. 1 – 8.
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