- Home
- Conference
- ICICMCT'23
- Article
A Synchronous Barrel Shifter Design Using Single Rail and hybrid Rail logic
Authors
1AssistantProfessor, ECE, IES College of Engineering, Chittilappilly, Kerala, India. 2Student, ECE, IES College of Engineering, Chittilappilly, Kerala, India.
Article Information
- DOI
- No DOI
- Organised By
- IES College of Engineering
- Conference Date
- 15 May 2023
- Pages
- 33-38
- Article Type
- Research Article
- Check for updates
- No DOI available for cross-reference
References
1. An asynchronous FPGA In view of Double/Single-Rail Cross breed Engineering ERSA'12 ShortPaper ZhengfanXia, Shota
Ishihara,Masanori Hariyama, and MichitakaKameyama GraduateSchoolof DataSciences,Tohoku College
2. S. M. Nowick, "Plan of a low-inertness asynchronous snake utilizing speculative finish," IEEProc.Comput. Digit.Techn., vol.143,no.
5,pp. 301-307, 1996.
3. K. K. Lai, "Novel offbeat fulfillment discovery for number-crunching data-paths," School Eng.,Taylor'sUniv., SubangJaya,Malaysia,
Rep.,2016.
4. K. K. Lai, E. C. Y. Chung, S.- L. L. Lu, and S. F. Quigley, "Plan of a low idleness asynchronousviper utilizing early consummation
recognition," J. Eng. Sci. Technol., vol. 9, no. 6, pp. 755-772,2014.
5. J.Sparsø,ProloguetoOffbeatCircuitPlan.Lyngby,Denmark:DTUFigure,2020.
6. T.-T.LiuandJ.M.Rabaey,"Factual examination and streamlining of asynchronous computer-ized circuits,"in Proc.IEEE eighteenth Int.Symp.
Offbeat CircuitsSyst.,2012,pp.1-8.
7. S.F.Oberman,"Plan issues in superior execution driftingpointarithmaticunits,"Ph.D.paper,Dept.Electr. Eng., Stanford Univ.,Stanford,CA,
USA,1996.
8. J.F.Palmer,B.W.Ravenel,andR.Nave,"Numericinformationprocessor,"GoogleLicensesUSRE33 629 E, 1982.
9. M. R. Pillmeier, M. J. Schulte, and E. G. Walters, III, "Plan alterna#tives for barrel shifters," inProc. Adv. Signal Interaction.
Calculations Archit. Execute. Int. Soc. Pick. Photon. XII, vol. 4791,2002, pp. 436-447.
10. Plan and Execution of Novel Multiplier utilizing Barrel Shifters Neeta Pandey Delhi Innova-tive College,SaurabhGuptaDelhi
MechanicalCollege,July 2015
11. B.K.MohantyandS.K.Patel,"Regiondelay-power proficient convey select viper"
12. P.Merollaetal.,"1,000,000Spiking-NeuronCoordinatedCircuitwithaVersatileCorrespon-dence Organization and Pointofinteraction,"
Science, vol.345,no.6197,2014,pp. 668673.
13. Stephen H. Unger, Offbeat Consecutive Exchanging Circuits, J. Wiley and Children, Inc., NewYork,NY, 1969.
14. D.EMullerandW.C.Bartky,"AHypothesisofasynchronousCircuits,"inRecordsofRegis-tering Research center of Harvard
College,1959,pp.204-243.
15. H. van Gageldonk et al., "An Offbeat Low-Power 80C51 Microcontroller," Proc. Int'l
Symp.HighlevelExplorationinOffbeatCircuitsandFrameworks(ASYNC98),IEEECSPress,1998,pp.96-107.
16. M. Davies et al., "A 72-Port 10G Ethernet Switch/Switch Utilizing Quasi-Delay-InsensitiveOffbeat Plan," Proc.Intl. Symp. on Offbeat
Circuits and Frameworks (ASYNC 14), 2014, pp.103-104.
17. J. Teifel and R. Manohar, "Exceptionally Pipelined Offbeat FPGAs," Proc. ACM/SIGDA Int.Symp.on FieldProgrammableDoorExhibits
(FPGA04), 2004,pp. 133-142.
Ishihara,Masanori Hariyama, and MichitakaKameyama GraduateSchoolof DataSciences,Tohoku College
2. S. M. Nowick, "Plan of a low-inertness asynchronous snake utilizing speculative finish," IEEProc.Comput. Digit.Techn., vol.143,no.
5,pp. 301-307, 1996.
3. K. K. Lai, "Novel offbeat fulfillment discovery for number-crunching data-paths," School Eng.,Taylor'sUniv., SubangJaya,Malaysia,
Rep.,2016.
4. K. K. Lai, E. C. Y. Chung, S.- L. L. Lu, and S. F. Quigley, "Plan of a low idleness asynchronousviper utilizing early consummation
recognition," J. Eng. Sci. Technol., vol. 9, no. 6, pp. 755-772,2014.
5. J.Sparsø,ProloguetoOffbeatCircuitPlan.Lyngby,Denmark:DTUFigure,2020.
6. T.-T.LiuandJ.M.Rabaey,"Factual examination and streamlining of asynchronous computer-ized circuits,"in Proc.IEEE eighteenth Int.Symp.
Offbeat CircuitsSyst.,2012,pp.1-8.
7. S.F.Oberman,"Plan issues in superior execution driftingpointarithmaticunits,"Ph.D.paper,Dept.Electr. Eng., Stanford Univ.,Stanford,CA,
USA,1996.
8. J.F.Palmer,B.W.Ravenel,andR.Nave,"Numericinformationprocessor,"GoogleLicensesUSRE33 629 E, 1982.
9. M. R. Pillmeier, M. J. Schulte, and E. G. Walters, III, "Plan alterna#tives for barrel shifters," inProc. Adv. Signal Interaction.
Calculations Archit. Execute. Int. Soc. Pick. Photon. XII, vol. 4791,2002, pp. 436-447.
10. Plan and Execution of Novel Multiplier utilizing Barrel Shifters Neeta Pandey Delhi Innova-tive College,SaurabhGuptaDelhi
MechanicalCollege,July 2015
11. B.K.MohantyandS.K.Patel,"Regiondelay-power proficient convey select viper"
12. P.Merollaetal.,"1,000,000Spiking-NeuronCoordinatedCircuitwithaVersatileCorrespon-dence Organization and Pointofinteraction,"
Science, vol.345,no.6197,2014,pp. 668673.
13. Stephen H. Unger, Offbeat Consecutive Exchanging Circuits, J. Wiley and Children, Inc., NewYork,NY, 1969.
14. D.EMullerandW.C.Bartky,"AHypothesisofasynchronousCircuits,"inRecordsofRegis-tering Research center of Harvard
College,1959,pp.204-243.
15. H. van Gageldonk et al., "An Offbeat Low-Power 80C51 Microcontroller," Proc. Int'l
Symp.HighlevelExplorationinOffbeatCircuitsandFrameworks(ASYNC98),IEEECSPress,1998,pp.96-107.
16. M. Davies et al., "A 72-Port 10G Ethernet Switch/Switch Utilizing Quasi-Delay-InsensitiveOffbeat Plan," Proc.Intl. Symp. on Offbeat
Circuits and Frameworks (ASYNC 14), 2014, pp.103-104.
17. J. Teifel and R. Manohar, "Exceptionally Pipelined Offbeat FPGAs," Proc. ACM/SIGDA Int.Symp.on FieldProgrammableDoorExhibits
(FPGA04), 2004,pp. 133-142.
Related Articles
Share Article
*Instagram doesn't support direct link sharing from web. Copy the link and share it in your Instagram story or post.