Auditing a GA-Optimized Chaotic Key Generator: Reconciling Simulation and Hardware Results Before Further Extension

Shajeela Beegom B A; Dr. Karthigai S

doi:10.59256/ijire.20260705004

Original Article

Auditing a GA-Optimized Chaotic Key Generator: Reconciling Simulation and Hardware Results Before Further Extension

Paper ID 1191
Volume 7, Issue 5
Pages 20-23
Published Online: September-October 2026

Open Access Peer Reviewed Crossref DOI

Authors

Shajeela Beegom B A¹
Dr. Karthigai S²

¹ ² Department of Computer Science, Vet Institute of Arts and Science (Co-Education) College, Tamil Nadu, India.

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Article Information

DOI: https://www.doi.org/10.59256/ijire.20260705004
Published In: Volume 7, Issue 5 (2026)
Published Online: September-October 2026
Pages: 20-23
Article Type: Original Article
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Citations

Shajeela Beegom B A, Dr. Karthigai S, “Auditing a GA-Optimized Chaotic Key Generator: Reconciling Simulation and Hardware Results Before Further Extension”, IJIRE-V7I5-20-23.

Auditing a GA-Optimized Chaotic Key Generator: Reconciling Simulation and Hardware Results Before Further Extension

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