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VLSI Implementation of HCA Based Median Filter with Noise Detection Architecture for EMG De- Noising
Authors
1 Student, M-tech in VLSI ECE, IES College of Engineering, Chittilappilly, Kerala, India. 2Assistant Professor Department of ECE, IES College of Engineering, Chittilappilly, Kerala, India.
Article Information
- DOI
- No DOI
- Organised By
- IES College of Engineering
- Conference Date
- 15 May 2023
- Pages
- 45-52
- Article Type
- Research Article
- Check for updates
- No DOI available for cross-reference
References
1. M. Marouf, L. Saranovac, and G. Vukomanovic, “Algorithm for EMG noise level approximation in ECG signals”, Biomedical Signal
Processing and Control, Vol. 34, pp. 158-165, 2017.
2. J. Too, A. R. Abdullah, N. M. Saad, N. M. Ali, and T. N. S. T. Zawawi, “Exploring the Relation Between EMG Pattern Recognition and
Sampling Rate Using Spectrogram”, Journal of Electrical Engineering & Technology, Vol. 14, No. 2, pp. 947-953, 2019.
3. Y. Ykuntam, Katta Pavani, K. Saladi, “Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI
circuit designs”, IEEE Xplore.2020.
4. V. G. Moshnyaga and K. Hashimoto, “An efficient implementation of 1-D median filter”, IEEE 52nd International Midwest Symposium
on Circuits and Systems, pp. 451-454, 2009.
5. SreenivaasMuthyala Sudhakar, Kumar P. Chidambaram and Earl E. Swartzlander Jr. “Hybrid Han-Carlson Adder”The University of
Texas at Austin, 2012.
6. M.L. Zhu and D.Y. Ge, “Image quality assessment based on deep learning with FPGA implementation”, Signal Processing: Image
Communication, Vol. 83, pp. 115780, 2020.
7. Sanny and V.K. Prasanna, “Energy-efficient median filter on FPGA”, In: Proc. of International Conf. on Reconfigurable Computing and
FPGAs (ReConFig), pp. 1-8, 2013.
8. Lin, W. T. Chen, Y. C. Chou, and P. Y. Chen, “A Novel Comparison-Free 1D Median Filter”, IEEE Transactions on Circuits and
Systems II: Express Briefs, pp. 1-1, 2019.
9. R. D. Chen, P. Y. Chen, and C. H. Yeh, “A lowpower architecture for the design of a onedimensional median filter”, IEEE Transactions
on Circuits and Systems II: Express Briefs, Vol. 62, No. 3, pp.266-270, 2014.
10. K. Rawwat, T. Darwish, and M. Bayoumi, “.A low power carry select adder with reduces area”, Proc. Of Midwest Symposium on
Circuits and Systems, pp. 218- 221, 2001
11. S. H. Lin, P. Y. Chen, and C. H. Lin, “Hardware design of an energy-efficient high-throughput median filter”, IEEE Transactions on
Circuits and Systems II: Express Briefs, Vol. 65, No. 11, pp. 1728-1
Processing and Control, Vol. 34, pp. 158-165, 2017.
2. J. Too, A. R. Abdullah, N. M. Saad, N. M. Ali, and T. N. S. T. Zawawi, “Exploring the Relation Between EMG Pattern Recognition and
Sampling Rate Using Spectrogram”, Journal of Electrical Engineering & Technology, Vol. 14, No. 2, pp. 947-953, 2019.
3. Y. Ykuntam, Katta Pavani, K. Saladi, “Design and analysis of High speed wallace tree multiplier using parallel prefix adders for VLSI
circuit designs”, IEEE Xplore.2020.
4. V. G. Moshnyaga and K. Hashimoto, “An efficient implementation of 1-D median filter”, IEEE 52nd International Midwest Symposium
on Circuits and Systems, pp. 451-454, 2009.
5. SreenivaasMuthyala Sudhakar, Kumar P. Chidambaram and Earl E. Swartzlander Jr. “Hybrid Han-Carlson Adder”The University of
Texas at Austin, 2012.
6. M.L. Zhu and D.Y. Ge, “Image quality assessment based on deep learning with FPGA implementation”, Signal Processing: Image
Communication, Vol. 83, pp. 115780, 2020.
7. Sanny and V.K. Prasanna, “Energy-efficient median filter on FPGA”, In: Proc. of International Conf. on Reconfigurable Computing and
FPGAs (ReConFig), pp. 1-8, 2013.
8. Lin, W. T. Chen, Y. C. Chou, and P. Y. Chen, “A Novel Comparison-Free 1D Median Filter”, IEEE Transactions on Circuits and
Systems II: Express Briefs, pp. 1-1, 2019.
9. R. D. Chen, P. Y. Chen, and C. H. Yeh, “A lowpower architecture for the design of a onedimensional median filter”, IEEE Transactions
on Circuits and Systems II: Express Briefs, Vol. 62, No. 3, pp.266-270, 2014.
10. K. Rawwat, T. Darwish, and M. Bayoumi, “.A low power carry select adder with reduces area”, Proc. Of Midwest Symposium on
Circuits and Systems, pp. 218- 221, 2001
11. S. H. Lin, P. Y. Chen, and C. H. Lin, “Hardware design of an energy-efficient high-throughput median filter”, IEEE Transactions on
Circuits and Systems II: Express Briefs, Vol. 65, No. 11, pp. 1728-1
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