Partial Product Reduction Using Fast Dadda Multiplier: A New Design Technique

1]. [B.Parhami, "Computer Arithmetic", Oxford University Press, 2000.
[2]. E. E. Swartzlander, Jr. and G. Goto, "Computer arithmetic," The Computer Engineering Handbook, V. G. Oklobdzija, ed., Boca
Raton, FL: CRC Press, 2002.
[3]. C. S. Wallace, “A Suggestion for a Fast Multiplier,” IEEE Transactions on Electronic Computers, Vol. EC-13, pp. 14-17, 1964.
[4]. Luigi Dadda, “Some Schemes for Parallel Multipliers,” Alta Frequenza, Vol. 34, pp. 349-356, August 1965.
[5]. K.C. Bickerstaff, E.E. Swartzlander, M.J. Schulte, Analysis of column compression multipliers, Proceedings of 15th IEEE Symposium
on Computer Arithmeitc,2001.
[6]. W. J. Townsend, Earl E. Swartzlander and J.A. Abraham, “A comparison of Dadda and Wallace multiplier delays”, Advanced Signal
Processing Algorithms, Architectures and Implementations XIII. Proceedings of the SPIE, vol. 5205, 2003, pages 552-560.
[7]. P. R. Cappello and K Steiglitz: A VLSI layout for a pipe-lined Dadda multiplier, ACM Transactions on Computer Systems,pp. 157-
174, 1983.
[8]. Bickerstaff, K.C.”Optimization of Column Compression Multipliers” Doctoral Dissertation, Dept. of Electrical and Computer
Engineering, University of Texas at Austin, Austin, Texas, 2007.
[9]. V. G. Oklobdzija and D.Villeger, “Improving Multiplier Design by Using Improved Column Compression Tree and Optimized Final
Adder in CMOS Technology”, IEEE transactions on Very Large Scale Integration (VLSI) systems, Vol. 3, no. 2, June 1995.
[10]. Paul F.Stelling, “Design strategies for optimal hybrid final adders in parallel multiplier”,Journal of VLSI signal processing, vol
14,pp,321-331,1996.
[11]. Sabyasachi Das and Sunil P.Khatri,"Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier",
International Conference on Integrated Circuit Design and Technology (ICICDT) May, 2007.
[12]. B.Ramkumar, Harish M Kittur and P.Mahesh Kannan, “ ASIC Implementation of Modified Faster Carry Save Adder”, European
Journal of Scientific Research, Vol. 42, Issue 1, 2010.
[13]. B.Ramkumar and Harish M Kittur , “ Low Power and Area Efficient Carry Select Adder”, IEEE Transactions on Very Large Scale
Integration (VLSI) systems, vol. 20, Issue2, pp.371-375, Feb 2012.
[14]. J. M. Rabaey, Digtal Integrated Circuits - A Design Perspective. Prentice Hall Press, 2001.
[15]. EncounterTM User Guide, February, 2006.