Partial Product Reduction Using Fast Dadda Multiplier: A New Design Technique

DOI

No DOI

Conference

Innovations in Computing, Materials and Communication Technologies

Organised By

IES College of Engineering

Conference Date

15 May 2023

Pages

110-115

Article Type

Research Article

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Multiplication is a one of main operation in most of Digital Signal Processing (DSP) applications. Multiple methodologies are employed to effect the multiplication of two numbers. The central focus of the Multiplier primarily revolves around four critical aspects that are crucial to establishing an effective multiplier: speed, power consumption, area, anchd accuracy. Primary requirement of error tolerant applications in digital system is low power consumption and high speed. The power consumption is reduced by truncating the least significant part of the multiplier. In processor, speed of multiplier defines the speed of digital signal processor. By designing of an effective Multiplier, we can enhance the performance of Micro-Processing System and Complex Digital Signal Processing System. We have different type of Multipliers, which are, Booth Multiplier, Wallace Tree Multiplier, Array Multiplier, Sequential Multiplier, Combinational Multiplier, Dadda Multiplier and Logarithm Multiplier. Among the tree based Multiplier, Dadda Multiplier is more efficient and widely used one. Dadda Multiplier is one of main Multiplier proposed by Dadda to reduce the partial products with minimum critical path delay. The proposed Fast Dadda multiplier uses a divide approach by dividing the LSP and MSP. In order to improve speed, carry propagation is minimized by performing both LSP and MSP separately and based on carry it is added in the final stage to produce the product.