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A VLSI-Based Multi-Level ECG Compression Method forHealth Care Applications
Authors
1Student, VLSI Design, Department of Electronics and Communication, IES College of Engineering / APJ Abdul Kalam Technological University, Kerala, India. 2Assistant Professor, Department of Electronics and Communication, IES College of Engineering / APJ Abdul Kalam Technological University, Kerala, India.
Article Information
- DOI
- No DOI
- Organised By
- IES College of Engineering
- Conference Date
- 15 May 2023
- Pages
- 88-94
- Article Type
- Research Article
- Check for updates
- No DOI available for cross-reference
Abstract
View PDFWearable sensor nodes generate a lot of data since they have characteristics for continuous monitoring. Additionally, as data transmission uses around 3/4 of the sensor node's power, power consumption is a significant barrier to these nodes' ability to maintain longer battery life. Wearable sensor nodes create and send a considerable quantity of data during intelligent long-term monitoring of any biological signal in wireless body area networks, boosting transmission power consumption. A lossless data compression method for an ECG signal monitoring system is suggested in order to decrease data storage and power use. In order to improve the bit compressing rate, a hybrid lossless multi-level compression technique based on Golomb-Rice coding and dictionary selection based on bitmask approach is presented. The majority of lossy techniques require an efficient preprocessing stage in order to identify the clinically important attributes with the lowest reconstruction error. As a result, computational workload increases. Furthermore, moving across domains requires a large storage space with a larger latency. In lossless compression, prediction-based methods utilizing Golomb-Rice encoding are employed. putting into practice an adaptive linear predictor and recording the projected difference with varying length.The implementation of adaptive Golomb-Rice entropy coding in an adaptive linear predictor built on VLSI is explained. Using a power-gating technique, compressed sensing develops a low-power FPGA-based compression architecture.
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