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Original Article
Hardware-Efficient Triple Modular Redundancy via Shared Arithmetic Resources
B. Gayathiri1
N. Peramlatha2
1 VLSI Design, Vandayar Engineering College, Thanjavur, Tamilnadu, India. 2 Assistant Professor, Vandayar Engineering College, Thanjavur, Tamilnadu, India.
Published Online: July-August 2026
Pages: 01-06
Cite this article
↗ https://www.doi.org/10.59256/ijire.20260704001
References
1. R. E. Lyons and W. Vanderkulk, "The use of triple-modular redundancy to improve computer reliability," IBM Journal of Research
and Development, vol. 6, no. 2, pp. 200-209, Apr. 1962, doi: 10.1147/rd.62.0200.
2. Xilinx, "Triple Module Redundancy Design Techniques for Virtex FPGAs," Application Note XAPP197, Rev. 1.0.1, July 2006.
3. Xilinx/AMD, "TMRTool Software Version 13.2 User Guide," UG156, Rev. 3.1.2, June 2017.
4. [4] F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda, "On the optimal design of triple modular redundancy logic for
SRAM-based FPGAs," in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2005, pp. 1290-1295,
doi: 10.1109/DATE.2005.229.
5. M. D. Berg, "Single Event Effects in FPGA Devices," NASA Electronic Parts and Packaging Program, 2015.
6. A. D. Booth, "A signed binary multiplication technique," Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, no. 2,
pp. 236-240, 1951, doi: 10.1093/qjmam/4.2.236.
7. C. S. Wallace, "A suggestion for a fast multiplier," IEEE Transactions on Electronic Computers, vol. EC-13, no. 1, pp. 14-17, Feb.
1964, doi: 10.1109/PGEC.1964.263830.
8. K. B. Jaiswal, N. Kumar V., P. Seshadri, and G. Lakshminarayanan, "Low power Wallace tree multiplier using modified full adder,"
in Proc. 3rd International Conference on Signal Processing, Communication and Networking (ICSCN), 2015, pp. 1-4, doi:
10.1109/ICSCN.2015.7219880.
9. V. Solanki, A. D. Darji, and H. Singapuri, "Design of low-power Wallace tree multiplier architecture using modular approach,"
Circuits, Systems, and Signal Processing, vol. 40, pp. 4407-4427, 2021, doi: 10.1007/s00034-021-01671-3.
10. Y. Wu, C. Chen, W. Xiao, X. Wang, C. Wen, J. Han, X. Yin, W. Qian, and C. Zhuo, "A survey on approximate multiplier designs
for energy efficiency: From algorithms to circuits," ACM Transactions on Design Automation of Electronic Systems, vol. 28, no. 6,
pp. 1-37, 2023, doi: 10.1145/3610291.
and Development, vol. 6, no. 2, pp. 200-209, Apr. 1962, doi: 10.1147/rd.62.0200.
2. Xilinx, "Triple Module Redundancy Design Techniques for Virtex FPGAs," Application Note XAPP197, Rev. 1.0.1, July 2006.
3. Xilinx/AMD, "TMRTool Software Version 13.2 User Guide," UG156, Rev. 3.1.2, June 2017.
4. [4] F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda, "On the optimal design of triple modular redundancy logic for
SRAM-based FPGAs," in Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE), 2005, pp. 1290-1295,
doi: 10.1109/DATE.2005.229.
5. M. D. Berg, "Single Event Effects in FPGA Devices," NASA Electronic Parts and Packaging Program, 2015.
6. A. D. Booth, "A signed binary multiplication technique," Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, no. 2,
pp. 236-240, 1951, doi: 10.1093/qjmam/4.2.236.
7. C. S. Wallace, "A suggestion for a fast multiplier," IEEE Transactions on Electronic Computers, vol. EC-13, no. 1, pp. 14-17, Feb.
1964, doi: 10.1109/PGEC.1964.263830.
8. K. B. Jaiswal, N. Kumar V., P. Seshadri, and G. Lakshminarayanan, "Low power Wallace tree multiplier using modified full adder,"
in Proc. 3rd International Conference on Signal Processing, Communication and Networking (ICSCN), 2015, pp. 1-4, doi:
10.1109/ICSCN.2015.7219880.
9. V. Solanki, A. D. Darji, and H. Singapuri, "Design of low-power Wallace tree multiplier architecture using modular approach,"
Circuits, Systems, and Signal Processing, vol. 40, pp. 4407-4427, 2021, doi: 10.1007/s00034-021-01671-3.
10. Y. Wu, C. Chen, W. Xiao, X. Wang, C. Wen, J. Han, X. Yin, W. Qian, and C. Zhuo, "A survey on approximate multiplier designs
for energy efficiency: From algorithms to circuits," ACM Transactions on Design Automation of Electronic Systems, vol. 28, no. 6,
pp. 1-37, 2023, doi: 10.1145/3610291.
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